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Features
• High-performance 3,3V EEPROM-based CPLD • 3,3V in-system programmable (ISP) • Built-in boundary-scan test (BST) circuitry • Supports JEDEC Jan standard test and programming language ((STAPL) JESD-71J
Technical Specifications
Part Nr.
Macrocells
PLD-Gates
Input
Output
max.
max.
EPM7032AETI44-7N
32
600
36
32
Terms of Delivery
Minimum order quantity: please see price list column "MOQ".